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91400 rm (im) tw no.5539-1/19 ver.1.00 61896 preliminary overview the lc866020c/16c/12c/08c microcontrollers are 8-bit single chip microcontrollers with the following on-chip functional blocks : - cpu : operable at a minimum bus cycle time of 0.5 s (microsecond) - on-chip rom maximum capacity : 20k bytes - on-chip ram capacity : 384 bytes - vfd automatic display controller/driver - 16-bit timer/counter (or two 8-bit timers) - 16- bit timer/pwm (or two 8-bit timers) - 4 channels 8-bit ad converter - two 8-bit synchronous serial interface circuits - 14-source 10-level vectored interrupt system all of the above functions are fabricated on a single chip. features (1) read-only memory (rom) : lc866020c 20480 8 bits lc866016c 16384 8 bits lc866012c 12288 8 bits LC866008C 8192 8 bits (2) random access memory (ram) : lc866020c/16c/12c/08c 384 8 bits (3) minimum bus cycle time : 0.5 s (using 12mhz cf resonator oscillation) bus cycle time means rom-read period. 8-bit single chip microcontroller with on-chip 20/16/12/08k-byte rom and 384-byte ram lc866020/16/12/08c ordering number : enn*5539 cmos ic
lc866020/16/12/08c no.5539-2/19 (4) minimum instruction cycle time : 1 s (using 12mhz cf resonator oscillation) rom data is accessed twice in a instruction cycle time. the operation of the microcomputers herein is about 1.7 times that of lc66000 series, our products in the same specified cycle time. (5) ports - input/output ports : 2 ports (16 terminals) - input/output port programmable in nibble units : 1 port (8 terminals) - input/output port programmable in a bit : 1 port (8 terminals) - input ports : 2 ports (8 port pins) - vfd output ports : 30 terminals - large current output for digit : 16 terminals - pull-down resistor option available (6) vfd automatic display controller - segment/digit output pattern programmable any segment/digit combination available vfd parallel-drive available - 16-step dimmer function available (7) ad converter - 4-channels 8-bit ad converter (8) serial interface - two 8-bit serial-interface circuits - lsb first/msb first function available - internal 8-bit baud-rate generator in common with two serial-interface circuits (9) timers - timer0 : 16-bit timer / counter with 2-bit prescaler + 8-bit programmable prescaler mode 0 : two 8-bit timers with programmable prescaler mode 1 : 8-bit timer with programmable prescaler + 8-bit counter mode 2 : 16-bit timer with programmable prescaler mode 3 : 16-bit counter the resolution of timer0 is 1 tcyc, the cycle time. - timer1 : 16-bit timer / pwm mode 0 : two 8-bit timers mode 1 : 8-bit timer + 8-bit pwm mode 2 : 16-bit timer mode 3 : variable bit pwm (9 to 16 bits) in mode 0 and mode 1, the resolution of timer1 and pwm is tcyc. in mode 2 and mode 3, the resolution is selectable by program ; tcyc or 1/2tcyc - base timer every 500ms overflow system for a clock application (using 32.768khz crystal oscillation for base timer clock) every 976 s, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.768khz crystal oscillation for base timer clock) the base timer clock selectable, 32.768khz crystal oscillation, system clock, and programmable prescaler output of timer0. (10) buzzer output - the buzzer sound frequency selectable ; 4khz, 2khz (using 32.768khz crystal oscillation for timer clock) (11) remote control receiver circuit (connected to the p73/int3/t0in terminal) - noise rejection function - polarity switching
lc866020/16/12/08c no.5539-3/19 (12) watchdog timer - the watchdog timer is taken on rc outside. - watchdog timer operation selectable : interrupt system, system reset (13) interrupt system - 14-source 10-level vectored interrupts : 1. external interrupt int0 (includes watchdog timer) 2. external interrupt int1 3. external interrupt int2, timer/counter t0l (lower 8 bits) 4. external interrupt int3, base timer 5. timer/counter t0h (upper 8 bits) 6. timer t1h /t1l 7. serial interface sio0 8. serial interface sio1 9. ad converter 10. vfd display controller, port 0 - interrupt priority control available the interrupt priority control register included. these microcomputers allows 3-level interrupt ; low-level, high-level and highest-level of multiplex interrupt. it can specify a low-level or a high-level interrupt priority from int2/t0l through vfd display controller/port 0 (the above interrupt number from 3 to 10). it can also specify a low-level or the highest-level interrupt priority to int0 and int1. (14) real-time service operation the real-time service (rts) functions the data-transfer between the special function registers at acknowledging the interrupt request. the rts starts within 1 cycle-time and completes within 5 cycle-times after occurring the interrupt request. (15) sub-routine stack levels - 128 levels (max.) : stack area included in ram area. (16) multiplication and division - 16 bits 8 bits (7 instruction cycle times) - 16 bits 8 bits (7 instruction cycle times) (17) 3 oscillation circuits - on-chip rc oscillation circuit using for the system clock - on-chip cf oscillation circuit using for the system clock - on-chip x?tal oscillation circuit using for the system clock and for time-base clock (18) standby function - halt mode function the halt mode is used to reduce the power dissipation. in this operation mode, the program execution is stopped. this operation mode can be released by the interrupt request signals or the system reset. - hold mode function the hold mode is used to stop all the oscillations ; the rc (internal), cf and x?tal oscillations. this mode can be released by the following conditions. reset terminal ( res ) set to low level. p70/int0/t0in, p71/int1/t0in terminals set to assigned level (programmable). port 0 terminal/terminals set to low level (programmable). (19) factory shipment dip64s delivery form qfp64e delivery form
lc866020/16/12/08c no.5539-4/19 (20) development tools - evaluation chip : lc866098 - eprom version : lc86e6032 - one time version : lc86p6032 - emulator : eva86000 + ecb866000 (evaluation chip board) + pod866000 (pod : dip64s) / pod866010 (pod : qip64e) pin assignment dip64s package dimension (unit : mm) 3071 sanyo : dip-64s(750mil) p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/buz p17/pwm test1 res xt1 xt2 vss cf1 cf2 vdd p80/an0 p81/an1 p82/an2 p83/an3 p70/int0 p71/int1 p72/int2/t0in p73/int3/t0in s0/t0 s1/t1 s2/t2 s3/t3 s4/t4 s5/t5 s6/t6 s7/t7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p07 p06 p05 p04 p03 p02 p01 p00 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 vp vddvpp s15/t15 s14/t14 s13/t13 s12/t12 s11/t11 s10/t10 s9/t9 s8/t8
lc866020/16/12/08c no.5539-5/19 pin assignment qip64e package dimension (unit : mm) 3159 sanyo : qip-64e s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 vp vddvpp p17/pwm p16/buz p15/sck1 p14/si1/sb1 p13/so1 p12/sck0 p11/si0/sb0 p10/so0 p07 p06 p05 p04 p03 p02 p01 p00 s0/t0 s1/t1 s2/t2 s3/t3 s4/t4 s5/t5 s6/t6 s7/t7 s8/t8 s9/t9 s10/t10 s11/t11 s12/t12 s13/t13 s14/t14 s15/t15 test1 res xt1 xt2 vss cf1 cf2 vdd p80/an0 p81/an1 p82/an2 p83/an3 p70/int0 p71/int1 p72/int2/t0in p73/int3/t0in 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
lc866020/16/12/08c no.5539-6/19 system block diagram interrupt control standby control ir rom pla cf rc x?tal clock generator pc base timer sio0 sio1 timer 0 timer 1 adc int0 to 3 noise filtter xram (128 bytes) port 1 port 7 port 8 high voltage output vfd controller bus interface acc b register c register psw rar ram stack pointer watch dog timer port 0 real time service alu
lc866020/16/12/08c no.5539-7/19 pin description pin name i/o functions option vss power pin (-) vdd power pin (+) vp power pin (-) for vfd output pulldown resistor vddvpp power pin (+) *1 port0 p00 to p07 i/o 8-bit input/output port input for port 0 interrupt input/output in nibble units input for hold release pullup resistor: provided/not provided output form: cmos/ n-channel open drain port1 p10 to p17 i/o 8-bit input/output port input/output can be specified in bit unit. other pin functions p10: sio0 data output p11: sio0 data input/bus inpu/output p12: sio0 clock input/output p13: sio1 data output p14: sio1 data input/bus input/output p15: sio1 clock input/output p16: buzzer output p17: timer 1 output (pwm output) output form: cmos/ n-channel open drain port7 4-bit input port other functions p70: int0 input / hold release / nch-tr. output for watchdog timer p71: int1 input / hold release p72: int2 input / timer 0 event input p73: int3 input with noise filter / timer 0 event input interrupt received form, vector address. rising falling rising/ falling h level l level vector p70 p71 - p73 i/o i int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable 03h 0bh 13h 1bh pullup resistor: provided/not provided port8 p80 to p83 i 4-bit input port other functions ad input port (4 port pins) s0/t0 to s6/t6 o output for vfd display controller segment/timing in common (usable for static output port at pulldown registor not provided.) pullup resistor: provided/not provided s7/t7 to s15/t15 o output for vfd display controller segment/timing with internal pulldown resistor in common. s16 to s29 o output for vfd display controller segment (usable for static output port at pulldown registor not provided.) pullup resistor: provided/not provided res i reset pin test1 o test pin should be left unconnected. fixed high level output. xt1 i input pin for 32.768khz crystal oscillation. in case of non use, connect to vdd. xt2 o output pin for 32.768khz crystal oscillation. in case of non use, should be left unconnected. cf1 i input pin for ceramic resonator oscillation cf2 o output pin for ceramic resonator oscillation * all of port options can be specified in bit unit.
lc866020/16/12/08c no.5539-8/19 * a state of pins at reset. pin name input/output mode a state of pullup resistor specified at pullup option ports 0,7 input fixed pullup resistor exist port 1 input programmable pullup resistor off pin name a state of p-channel transistor s0/t0 to s15/t15 p-channel transistor off s16 to s29 p-channel transistor off *1 connect like the following figure to reduce noise into a vdd terminal shorten the vdd terminal to the vddvpp terminal. power supply vdd vss vddvpp lsi
lc866020/16/12/08c no.5539-9/19 1. absolute maximum ratings at vss=0v and ta=25 c ratings parameter symbol pins conditions vdd[v] min. typ. max. unit supply voltage vddmax vdd, vddvpp vdd= vddvpp -0.3 +7.0 vi(1) ports 71,72,73 port 8 res -0.3 vdd+0.3 input voltage vi(2) vp vdd-45 vdd+0.3 output voltage vo s0/t0 to s15/t15 s16 to s29 vdd-45 vdd+0.3 input/output voltage vio ports 0,1,70 -0.3 vdd+0.3 v ioph(1) ports 0,1 cmos output for each pin. -4 ioph(2) s0/t0 to s15/t15 for each pin. -30 peak output current ioph(3) s16 to s29 for each pin. -15 ioah(1) port 0 total all pins. -10 ioah(2) port 1 total all pins. -10 high level output current total output current ioah(3) s0/t0 to s15/t15 s16 to s29 total all pins. -130 iopl(1) ports 0,1 at each pin. 20 peak output current iopl(2) port 70 at each pin. 15 ioal(1) port 0 total all pins. 40 low level output current total output current ioal(2) ports 1,70 total all pins. 40 ma pdmax(1) dip64s ta=-30 to +70 c 670 maximum power dissipation pdmax(2) qfp64e ta=-30 to +70 c 380 mw operating temperature range topg -30 +70 storage temperature range tstg -65 +150 c
lc866020/16/12/08c no.5539-10/19 2. recommended operating range at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit vdd(1) 0.98 s t cyc 400 s 4.5 6.0 operating supply voltage range vdd(2) vdd 3.9 s t cyc 400 s 2.5 6.0 hold voltage vhd vdd ram and registers contain data at hold mode 2.0 6.0 pulldown voltage vp vp 2.5 - 6.0 -35 vdd vih(1) port 0 (schumitt) output disable 2.5 - 6.0 0.4vdd +0.9 vdd vih(2) port 1 ports 72, 73 (schumitt) output disable 2.5 - 6.0 0.75vdd vdd vih(3) port 70 port input/interrupt port 71 res (schumitt) output n-channel tr. off 2.5 - 6.0 0.75vdd vdd vih(4) port 70 watchdog timer input output n-channel tr. off 2.5 - 6.0 0.9vdd vdd input high voltage vih(5) port 8 2.5 - 6.0 0.75vdd vdd vil(1) port 0 (schumitt) output disable 2.5 - 6.0 vss 0.2vdd vil(2) port 1 ports 72, 73 (schumitt) output disable 2.5 - 6.0 vss 0.25vdd vil(3) port 70 port input/interrupt port 71 res (schumitt) n-channel tr. off 2.5 - 6.0 vss 0.25vdd vil(4) port 70 watchdog timer n-channel tr. off 2.5 - 6.0 vss 0.8vdd -1.0 input low voltage vil(5) port 8 2.5 - 6.0 vss 0.25vdd v 4.5 - 6.0 0.98 400 operation cycle time t cyc 2.5 - 6.0 3.9 400 s fmcf(1) cf1,cf2 12mhz (ceramic resonator oscillation) refer to figure 1 4.5 - 6.0 11.76 12 12.24 fmcf(2) cf1,cf2 3mhz (ceramic resonator oscillation) refer to figure 1 2.5 - 6.0 2.94 3 3.06 fmrc rc oscillation 2.5 - 6.0 0.4 0.8 3.0 mhz oscillation frequency range (note 1) fsxtal xt1, xt2 32.768khz (x?tal oscillation) refer to figure 2 2.5 - 6.0 32.768 khz tmscf(1) cf1,cf2 12mhz (ceramic resonator oscillation) refer to figure 3 4.5 - 6.0 0.02 0.2 4.5 - 6.0 0.1 1 tmscf(2) cf1,cf2 3mhz (ceramic resonator oscillation) refer to figure 3 2.5 - 6.0 0.1 3 ms 4.5 - 6.0 1 1.5 oscillation stabilizing time period (note 1) tssxtal xt1, xt2 32.768khz (x?tal oscillation) refer to figure 3 2.5 - 6.0 1 3 s (note 1) the oscillation constant is shown on table 1 and table 2.
lc866020/16/12/08c no.5539-11/19 3. electrical characteristics at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) port 1 port 0 without pullup mos tr. output disable pull-up mos tr. off vin=vdd (including the off- leak current of the output tr.) 2.5 - 6.0 1 iih(2) port 7 without pullup mos tr. port 8 vin=vdd 2.5 - 6.0 1 input high current iih(3) res vin=vdd 2.5 - 6.0 1 iil(1) port 1 port 0 without pullup mos tr. output disable pull-up mos tr. off vin=vss (including the off- leak current of the output tr.) 2.5 - 6.0 -1 iil(2) port 7 without pullup mos tr. port 8 vin=vss 2.5 - 6.0 -1 input low current iil(3) res vin=vss 2.5 - 6.0 -1 a voh(1) ioh=-1.0ma 4.5 - 6.0 vdd-1 voh(2) cmos output of ports 0, 1 ioh=-0.1ma 2.5 - 6.0 vdd-0.5 voh(3) ioh=-20ma 4.5 - 6.0 vdd-1.8 voh(4) s0/t0 to s15/t15 ioh=-1.0ma the current of each pin is not over 1ma 2.5 - 6.0 vdd-1 voh(5) ioh=-5ma 4.5 - 6.0 vdd-1.8 output high voltage voh(6) s16 to s29 ioh=-1.0ma the current of each pin is not over 1ma 2.5 - 6.0 vdd-1 vol(1) iol=10ma 4.5 - 6.0 1.5 vol(2) iol=1.6ma the total current of the ports 0,1 is not over 40ma 4.5 - 6.0 0.4 vol(3) ports 0, 1 iol=-1.0ma the current of each pin is not over 1ma 2.5 - 6.0 0.4 vol(4) iol=1ma 4.5 - 6.0 0.4 output low voltage vol(5) port 70 iol=0.5ma 2.5 - 6.0 0.4 v voh=0.9vdd 4.5 - 6.0 15 40 70 pull-up mos tr. resistance rpu ports 0, 1 port 7 voh=0.9vdd 2.5 - 4.5 25 70 150 k ? ioff(1) output p-channel tr. off vout=vss 2.5 - 6.0 -1 output off- leakage current ioff(2) s0/t0 to s6/t6 s16 to s29 (without pull down resistor.) output p-channel tr. off vout=vdd-40v 2.5 - 6.0 -30 a pulldown transistor resistor rpd s0/t0 to s15/t15 s16 to s29 (with pull down resistor.) output p-channel tr. off vout=3v vp=-30v 5.0 60 100 200 k ? hysteresis voltage vhis ports 0, 1 port 7 res output disable 2.5 - 6.0 0.1vdd v pin capacitance cp all pins f=1mhz terminals other then unloaded terminals set to vin=vss ta=25 c 2.5 - 6.0 10 pf
lc866020/16/12/08c no.5539-12/19 4. serial input/output characteristics at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit cycle t ckcy (1) 2 low level pulse width t ckl (1) 1 input clock high level pulse width t ckh (1) sck0, sck1 refer to figure 5. 2.5 - 6.0 1 cycle t ckcy (2) 2 low level pulse width t ckl (2) 1/2tckcy serial clock output clock high level pulse width t ckh (2) sck0, sck1 use a pull-up resistor (1k ? ) when an open drain output. refer to figure 5 2.5 - 6.0 1/2tckcy t cyc 4.5 - 6.0 0.1 data set up time t ick 2.5 - 6.0 0.4 4.5 - 6.0 0.1 serial input data hold time t cki si0, si1 sb0,sb1 data set-up to sck0, 1. data hold from sck0, 1. refer to figure 5. 2.5 - 6.0 0.4 4.5 - 6.0 7/12tcyc +0.2 output delay time (external serial clock) t cko(1) 2.5 - 6.0 7/12tcyc +1 4.5 - 6.0 1/3tcyc +0.2 serial output output delay time (internal serial clock) t cko(2) so0, so1 sb0,sb1 use a pull-up resistor (1k ? ) when an open drain output. data set-up to sck0, 1 falling data hold from sck0, 1 falling refer to figure 5 2.5 - 6.0 1/3tcyc +1 s 5. pulse input conditions at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0, int1 int2/t0in interrupt acceptable timer0-countable 2.5 - 6.0 1 tpih(2) tpil(2) int3/t0in (the noise rejection clock is selected to 1/1.) interrupt acceptable timer0-countable 2.5 - 6.0 2 tpih(3) tpil(3) int3/t0in (the noise rejection clock is selected to 1/64.) interrupt acceptable timer0-countable 2.5 - 6.0 128 t cyc high/low level pulse width tpil(4) res reset acceptable 2.5 - 6.0 200 s
lc866020/16/12/08c no.5539-13/19 6. ad converter characteristics at ta=-30 c to + 70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 8 bit absolute precision et (note 2) 1.5 lsb ad conversion time = 16 tcyc (adcr2=0) (note 3) 15.68 (tcyc= 0.98 s) 65.28 (tcyc= 4.08 s) conversion time tcad ad conversion time = 32 tcyc (adcr2=1) (note 3) 4.5 - 6.0 31.36 (tcyc= 0.98 s) 130.56 (tcyc= 4.08 s) s analog input voltage range vain 4.5 - 6.0 vss vdd v iainh vain=vdd 4.5 - 6.0 1 analog port input current iainl an0 - an3 vain=vss 4.5 - 6.0 -1 a (note 2) absolute precision excepts quantizing error (1/2 lsb). (note 3) the conversion time means the time from executing the ad conversion instruction to setting the complete digital conversion value to the register.
lc866020/16/12/08c no.5539-14/19 7. current dissipation characteristics at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddop(1) fmcf=12mhz ceramic resonator oscillation fsx?tal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 4.5 - 6.0 10 20 iddop(2) 4.5 - 6.0 3 6 iddop(3) fmcf=3mhz ceramic resonator oscillation fsx?tal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 2.5 - 4.5 1.5 5 iddop(4) 4.5 - 6.0 0.7 1.4 iddop(5) fmcf=0hz (when oscillation stops) fsx?tal=32.768khz crystal oscillation system clock : rc oscillation 2.5 - 4.5 0.4 1.2 ma iddop(6) 4.5 - 6.0 35 70 current dissipation during basic operation (note 4) iddop(7) vdd fmcf=0hz (when oscillation stops) fsx?tal=32.768khz crystal oscillation system clock : 32.768khz internal rc oscillation stops 2.5 - 4.5 15 50 a continue.
lc866020/16/12/08c no.5539-15/19 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddhalt(1) halt mode fmcf=12mhz ceramic resonator oscillation fsx?tal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 4.5 - 6.0 5 10 iddhalt(2) 4.5 - 6.0 1.8 4.6 iddhalt(3) halt mode fmcf=3mhz ceramic resonator oscillation fsx?tal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 2.5 - 4.5 0.8 2.5 ma iddhalt(4) 4.5 - 6.0 400 800 iddhalt(5) halt mode fmcf=0hz (when oscillation stops) fsx?tal=32.768khz crystal oscillation system clock : rc oscillation 2.5 - 4.5 200 600 iddhalt(6) 4.5 - 6.0 20 60 current dissipation in halt mode (note 4) iddhalt(7) vdd halt mode fmcf=0hz (when oscillation stops) fsx?tal=32.768khz crystal oscillation system clock : 32.768khz internal rc oscillation stops 2.5 - 4.5 7 40 iddhold(1) 4.5 - 6.0 0.05 30 current dissipation in hold mode (note 4) iddhold(2) vdd hold mode 2.5 - 4.5 0.02 20 a (note 4) the currents of the output transistors and the pull-up mos transistors are ignored.
lc866020/16/12/08c no.5539-16/19 table 1. ceramic resonator oscillation recommended constant (main clock) oscillation type maker oscillator c1 c2 csa12.0mtz 33pf 33pf murata cst12.0mtw on chip 12mhz ceramic resonator oscillation kyocera kbr-12.0m 33pf 33pf csa3.00mg 33pf 33pf murata cst3.00mgw on chip 3mhz ceramic resonator oscillation kyocera kbr-3.0ms 47pf 47pf * both c1 and c2 must use k rank (10%) and sl characteristics. table 2. crystal oscillation recommended constant (sub clock) oscillation type maker oscillator c3 c4 dai sinku dt-38(1ta252e00) 18pf 18pf 32.768khz crystal oscillation kyocera kf-38g-13p0200 4pf 4pf * both c3 and c4 must use j rank (5%) and ch characteristics. (it is about the application which is not in need of high precision. use k rank (10%) and sl characteristics.) (notes) since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the osci llation pins as possible with the shortest possible pattern length. if you use other oscillators herein, we provide no guarantee for the characteristics. figure 1 main-clock circuit figure 2 sub-clock circuit ceramic resonator oscillation crystal oscillation cf1 cf2 c2 cf c1 xt1 xt2 c4 x?tal c3
lc866020/16/12/08c no.5539-17/19 < reset time and oscillation stabilizing time. > < hold release signal and oscillation stabilizing time. > figure 3 oscillation stabilizing time power suppl y res interrnal rc resonator oscillation cf1, cf2 operation mode vdd vdd limit 0v reset time tmscf unfixed reset instruction execution mode hold release signal interrnal rc resonator oscillation xt1, xt2 operation mode valid tmscf hold instruction execution mode xt1, xt2 cf1, cf2 tssxtal tssxtal
lc866020/16/12/08c no.5539-18/19 figure 4 reset circuit figure 5 serial input / output test condition figure 6 pulse input timing condition (note) fix the value of cres, rres that is sure to reset until 200 s, after power supply has been over inferior limit of supply voltage. c res vdd r res res so0, so1 sb0, sb1 si0 si1 sck0 sck1 50pf 1k ? vdd tcko tcki tick tckh tckl tckcy 0.5vdd tpih tpil
lc866020/16/12/08c no.5539-19/19 memo: ps

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